Short channel effects (SCE) produced in channel regions positioned under the gate of a transistor give rise to high threshold voltages Vt and result in reduced drive current at identical off current. Trigate devices have lower Vt due to the gate wrapping around on three sides of the fin's gate region improving its SCE. However, the bottom ungated region of the fin can contribute to SCE if the peak of the source/drain tip junction reaches below the plane of the gated region. There is a need, therefore, to mitigate short channel effects in a trigate device typically manufactured on bulk silicon.